| August 05, 2026 |
The New PC-3000 Flash Software Ver. 9.4.6 has been released! |
The new PC-3000 Flash software update version 9.4.6 is now available!
This release delivers a broader resource base, new operation modes, and built-in Solution Database integration. We've also added fresh XORs and advanced ReadRetries for the latest Intel and Samsung memory chips, giving you the power to tackle complex data recovery cases that were previously out of reach.
To get the new update, please download it from the ACE Lab Portal https://ts.acelab.eu.com/files/ or get in touch via service@acelab.eu.com.
A LIST OF THE MAIN ENHANCEMENTS
| ADDED |
a new Read Retry algorithm for Intel NAND chips (ID = 56) |
| ADDED |
a new Read Retry algorithm for Samsung 3D TLC V4 NAND chips (ID = 57) |
| ADDED |
a new Read Retry algorithm for Samsung 3D TLC V5 NAND chips (ID = 58) |
| ADDED |
a new Read Retry algorithm for Samsung 3D TLC V6 NAND chips (ID = 59) |
| ENHANCED |
Flash Solution Center has been integrated into PC-3000 software. The opening button is located on the main PC-3000 Flash toolbar: |
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| "Solution Base" mode start button |
This mode includes a filter and lets you view the solution structure based on the operations performed and their parameters:
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| "Solution Base" mode overview |
| ADDED |
an ability to add customer monolith layouts to a personal database that is not overwritten during software updates. To get started, you need to specify the path to the personal database file. By default, the file is located in the software installation directory. The file name is "USERMONO.FDB." |
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| Specifying the path to the personal monolith database file |
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| "Add Monolith" mode |
| ADDED |
full support for 4K displays with a scaling ratio other than 100% to the "BitMap" mode used in the "Bad Bytes Cutting" preparation method |
| ADDED |
the ability to specify a time delay after power-on before performing any operation. This feature is necessary in some cases when working with monolithic storage devices with an active controller, as it allows the system to wait for the controller to finish communicating with the memory chip after power-on and avoid a bus conflict: |
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| The default delay is 0 seconds |
| ADDED |
an ability to choose a specific page or map with pages for "Automatic ECC detection with ReadRetry mode": |
 |
| ENHANCED |
the "Add Translator" mode to support blocks larger than 65,536 sectors. |
| IMPROVED |
the "Image Based on Data Analysis (FAT32)" mode to support large data blocks (larger than 100 MB) |
| ADDED |
new Static XOR:
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| ADDED |
new Dynamic XOR:
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| ADDED |
new Memory chips, read parameters:
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| ADDED |
new ECC formats:
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